clk rst o_mem_act i_mem_act lock g_sync st_spare1 st_spare2
lst_data dt_pres clink cmd_str_30 cmd_str_60
blk_str ad_str wr_dt_str rd_dt_str l1 rd_evt cal_str sync usr_rst 
start_pl inc_add data_width 
op_mode3 op_mode2 op_mode1 op_mode0
daq_format1 daq_format0
in_play_rec en_in_mem
out_play_rec en_out_mem
p_r_mode ct_spare1 ct_spare2 
clk30_in3 clk30_in2 clk30_in1 clk30_in0
clk15 clk8 clk4 clk2
dlink next_data 
buf_add03 buf_add02 buf_add01 buf_add00
buf_add13 buf_add12 buf_add11 buf_add10
data_io15 data_io14 data_io13 data_io12 data_io11 data_io10
data_io9 data_io8 data_io7 data_io6 data_io5 
data_io4 data_io3 data_io2 data_io1 data_io0
soft_led3 soft_led2 soft_led1 soft_led0
run_mode_led non_run_mode_led raw_data_led one_word_data_led
two_word_data_led in_play_rec_led 
en_in_mem_led en_out_play_rec_led en_out_mem_led 
single_mode_led continuous_mode_led 
glink_not_ready_led glink_not_sync_led
i_mem_act_led o_mem_act_led rx_signal_detect_n
glink_reset_n dclk_in dclk_out done spare1 spare2