-- VHDL netlist generated by SCUBA 4.1
-- Wed Mar 26 15:23:00 1997
-- changes: Armin Karcher; 4/3/97:
--	tied unused addresses to vhi instead of to AD1, this reduces fanout
--	include ORCA library for simulation
library IEEE;
--library ORCA;                            --  comment out for synthesis
use IEEE.std_logic_1164.all;
--use ORCA.orcacomp.all;                   --  comment out for synthesis

entity sdpram is
    port (waddr: in std_logic_vector(1 downto 0); datain: in std_logic_vector(31 downto 0); 
        clk: in std_logic; wren: in std_logic; raddr: in std_logic_vector(1 downto 0); 
        dataout: out std_logic_vector(31 downto 0));
end sdpram;

architecture Structure of sdpram is

    -- internal signal declarations
    signal scuba_vhi: std_logic;

    -- local component declarations
    component DCF16X2
        port (AD0: in std_logic; AD1: in std_logic; AD2: in std_logic; 
            AD3: in std_logic; DI0: in std_logic; DI1: in std_logic; CK: in std_logic; 
            WREN: in std_logic; WPE: in std_logic; RAD0: in std_logic; 
            RAD1: in std_logic; RAD2: in std_logic; RAD3: in std_logic; 
            RDO0: out std_logic; RDO1: out std_logic; DO0: out std_logic; 
            DO1: out std_logic);
    end component;
    component VHI
        port (Z: out std_logic);
    end component;

begin
    -- component instantiation statements
    mem_0_0_15: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(30), DI1=>datain(31), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(30), RDO1=>dataout(31), DO0=>open, DO1=>open);

    mem_0_1_14: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(28), DI1=>datain(29), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(28), RDO1=>dataout(29), DO0=>open, DO1=>open);

    mem_0_2_13: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(26), DI1=>datain(27), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(26), RDO1=>dataout(27), DO0=>open, DO1=>open);

    mem_0_3_12: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(24), DI1=>datain(25), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(24), RDO1=>dataout(25), DO0=>open, DO1=>open);

    mem_0_4_11: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(22), DI1=>datain(23), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(22), RDO1=>dataout(23), DO0=>open, DO1=>open);

    mem_0_5_10: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(20), DI1=>datain(21), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(20), RDO1=>dataout(21), DO0=>open, DO1=>open);

    mem_0_6_9: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(18), DI1=>datain(19), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(18), RDO1=>dataout(19), DO0=>open, DO1=>open);

    mem_0_7_8: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(16), DI1=>datain(17), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(16), RDO1=>dataout(17), DO0=>open, DO1=>open);

    mem_0_8_7: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(14), DI1=>datain(15), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(14), RDO1=>dataout(15), DO0=>open, DO1=>open);

    mem_0_9_6: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(12), DI1=>datain(13), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(12), RDO1=>dataout(13), DO0=>open, DO1=>open);

    mem_0_10_5: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(10), DI1=>datain(11), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(10), RDO1=>dataout(11), DO0=>open, DO1=>open);

    mem_0_11_4: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(8), DI1=>datain(9), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(8), RDO1=>dataout(9), DO0=>open, DO1=>open);

    mem_0_12_3: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(6), DI1=>datain(7), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(6), RDO1=>dataout(7), DO0=>open, DO1=>open);

    mem_0_13_2: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(4), DI1=>datain(5), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(4), RDO1=>dataout(5), DO0=>open, DO1=>open);

    mem_0_14_1: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(2), DI1=>datain(3), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(2), RDO1=>dataout(3), DO0=>open, DO1=>open);

    scuba_vhi_inst: VHI
        port map (Z=>scuba_vhi);

    mem_0_15_0: DCF16X2
        port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>scuba_vhi, AD3=>scuba_vhi, 
        DI0=>datain(0), DI1=>datain(1), CK=>clk, WREN=>wren, WPE=>scuba_vhi, 
        RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>scuba_vhi, RAD3=>scuba_vhi, 
        RDO0=>dataout(0), RDO1=>dataout(1), DO0=>open, DO1=>open);

end Structure;