----------------------------------------------------------------------------
-- Lawrence Berkeley National Laboratory (c) 1997
-- BaBar Trigger Electronics
----------------------------------------------------------------------------
-- Description:  
--    selects header type or data, converts parallel to serial
----------------------------------------------------------------------------
-- Structure:
-- par2ser
-- mux:	-- select memory data header, daq data header (first or second word)
--	   or data.
-- shift_reg:	-- convert mux output from parallel to serial
----------------------------------------------------------------------------
-- Author:   Armin Karcher
-- History:
--    Karcher    03/97 - First Version
-- Karcher 6-2-98 - changed MUX process to two-stage, added delay to latch
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

----------------------------------------------------------------------------
--PORT DECLARATION
----------------------------------------------------------------------------

entity par2ser is
  port	(clk 	: in  std_logic;	-- clk60 input, distributed
	rst 	: in  std_logic;	-- global reset
	latch   : in  std_logic;    -- load shift register after 2 ticks
	dt_sel	: in  std_logic_vector(2 downto 0);  -- select data/header
	tag	: in  std_logic_vector(4 downto 0);  -- subcommand
	cmd	: in  std_logic_vector(4 downto 0);  -- command
	hdr	: in  std_logic_vector(31 downto 0); -- DAQ header
	data_in	: in  std_logic_vector(15 downto 0); -- data
	dlink : out  std_logic			     -- serial data out
        );
end par2ser;

architecture rtl of par2ser is

----------------------------------------------------------------------------
--SIGNAL DECLARATION
----------------------------------------------------------------------------
  signal reg_val: std_logic_vector(15 downto 0); -- final output of mux
  signal reg_int_ev: std_logic_vector(15 downto 0); -- intermediate mux (event)
  signal reg_int_st: std_logic_vector(15 downto 0); -- intermediate mux (status)
  signal shift  : std_logic_vector(14 downto 0); -- contents of shift register
  signal latch_1del: std_logic;	 -- load shift register after 1 tick 
  signal latch_2del: std_logic;	 -- latch delayed: load shift register now

begin
 
----------------------------------------------------------------------------
--PROCESS DECLARATION
---------------------------------------------------------------------------- 

mux: process (clk,rst)
  begin
    if (rst = '1') then
      reg_val <= "0000000000000000";
      reg_int_ev <= "0000000000000000";
      reg_int_st <= "0000000000000000";
    elsif (clk'event and clk = '1') then
      if (dt_sel(0) = '1') then
        reg_int_st(15) <= data_in(0);     -- synchronous latch
        reg_int_st(14) <= data_in(1);     -- latch board data
        reg_int_st(13) <= data_in(2);    
        reg_int_st(12) <= data_in(3);  
        reg_int_st(11) <= data_in(4); 
        reg_int_st(10) <= data_in(5); 
        reg_int_st(9) <= data_in(6); 
        reg_int_st(8) <= data_in(7); 
        reg_int_st(7) <= data_in(8); 
        reg_int_st(6) <= data_in(9);   
        reg_int_st(5) <= data_in(10); 
        reg_int_st(4) <= data_in(11);
        reg_int_st(3) <= data_in(12); 
        reg_int_st(2) <= data_in(13); 
        reg_int_st(1) <= data_in(14); 
        reg_int_st(0) <= data_in(15); 
      else
        reg_int_st(15) <='1'; --latch status header
        reg_int_st(14) <='0';    
        reg_int_st(13) <= cmd(4);  
        reg_int_st(12) <= cmd(3);  
        reg_int_st(11) <= cmd(2);  
        reg_int_st(10) <= cmd(1);  
        reg_int_st(9) <= cmd(0);
        reg_int_st(8) <='0';    
        reg_int_st(7 downto 3) <= tag;  
        reg_int_st(2 downto 0) <="000";    
      end if;

      if (dt_sel(1) = '0') then
        reg_int_ev <= hdr(31 downto 16); -- latch upper event header bits  
      else
        reg_int_ev <= hdr(15 downto 0); -- latch lower event header bits
      end if;

      if (dt_sel(2) = '0' OR dt_sel(0) = '1') then
        reg_val <= reg_int_st;    -- board data data
      else
        reg_val <= reg_int_ev;    -- event headers
      end if;

    end if;
  end process;

 shift_reg: process (clk,rst)
  begin
    if (rst = '1') then
      shift <= "000000000000000";
      latch_1del <= '0';
      latch_2del <= '0';
    elsif (clk'event and clk = '1' ) then
      latch_1del <= latch;
      latch_2del <= latch_1del;
      if (latch_2del = '1') then
        shift <= reg_val(14 downto 0);     -- synchronous latch
        dlink <= reg_val(15);
      else
        dlink <= shift(14);
        shift(14) <= shift(13);
        shift(13) <= shift(12);
        shift(12) <= shift(11);
        shift(11) <= shift(10);
        shift(10) <= shift(9);
        shift(9) <= shift(8);
        shift(8) <= shift(7);
        shift(7) <= shift(6);
        shift(6) <= shift(5);
        shift(5) <= shift(4);
        shift(4) <= shift(3);
        shift(3) <= shift(2);
        shift(2) <= shift(1);
        shift(1) <= shift(0);
        shift(0) <= '0';
      end if;
    end if;
  end process;

end rtl;