---------------------------------------------------------------------------- -- Lawrence Berkeley National Laboratory (c) 1997 -- BaBar Trigger Electronics ---------------------------------------------------------------------------- -- Description: -- This entity contains all logic for the dlink fast control interface. -- A serial data stream, consisting of a header and data field is sent. -- There are two different header and data formats: memory data, consisting -- of a two byte header and 2 or 4 byte of data, or DAQ data, sent on a -- read event, consisting of a 4 byte header and a subsystem specific data -- field. -- This entity might possibly profit from the nfl structure, but previous -- versions have completed successful without the nfl prefix. ---------------------------------------------------------------------------- -- Structure: -- dlink_ctl -- sm0_dlink -- state machine, controlling the latching of header and data. -- par2ser -- essentially a shift register to convert the parrallel data -- into serial data. This entity also contains a mux, selecting -- which header or data is sent. -- latch16 -- latches the data bus once data is valid. -- -- sync_or -- synchronous or for data valid signal ---------------------------------------------------------------------------- -- Timing: -- Output data stream is generated once the first data word is latched. -- following data words have to be presented no later than 12 ticks after -- a valid next data. ---------------------------------------------------------------------------- -- Author: Armin Karcher -- History: -- Karcher 03/97 - First Version -- Karcher 6/4/97 - added FF for dt_pres, lst_data to acomodate DIN ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------------- --PORT DECLARATION ---------------------------------------------------------------------------- entity dlink_ctl is port( clk : in std_logic; -- clk60 input, distributed rst : in std_logic; -- global reset clk_30 : in std_logic; -- clk30 lst_data : in std_logic; -- last DAQ data word rd_blk : in std_logic; -- block read blk_done : in std_logic; -- block read done dt_pres : in std_logic; -- data present reg_data_vld : in std_logic; -- csr read data present dt_lng : in std_logic; -- data long (4 byte transfer) rd_evt_i : in std_logic; -- read event (valid on cmd_str) cmd_str : in std_logic; -- command strobe rd_dt_str : in std_logic; -- read data strobe data_bus_i : in std_logic_vector(15 downto 0); -- data bus hdr : in std_logic_vector(31 downto 0); -- read event -- header cmd : in std_logic_vector(4 downto 0); -- latched command tag : in std_logic_vector(4 downto 0); -- latched subcmd st_spare1 : in std_logic; -- board ID st_spare2 : in std_logic; -- board ID dlink : out std_logic; -- serial data stream rd_inc : out std_logic; -- increment block counter dl_rd : out std_logic; -- next_data : out std_logic -- data latched, ready for ); -- next data end dlink_ctl; architecture rtl of dlink_ctl is ---------------------------------------------------------------------------- --SIGNAL DECLARATION ---------------------------------------------------------------------------- signal lst_data_l: std_logic; -- last data (latched) signal dt_pres_l: std_logic; -- data present (latched) signal data_vld: std_logic; -- register data present signal data_vld_i: std_logic; -- data present (combination from external -- signal and csr_data_valid. signal dt_sel: std_logic_vector(0 to 2); --select type of header or data signal latch: std_logic; -- latch data signal data: std_logic_vector(0 to 15); -- internal data ---------------------------------------------------------------------------- --COMPONENT DECLARATION ---------------------------------------------------------------------------- component sm0_dlink port( clk : in std_logic; rst : in std_logic; clk_30 : in std_logic; data_vld : in std_logic; lst_data : in std_logic; dt_lng : in std_logic; rd_blk : in std_logic; -- block read blk_done : in std_logic; -- block done rd_evt : in std_logic; cmd_str : in std_logic; rd_dt_str : in std_logic; -- read data strobe reg_acc : in std_logic; st_spare1 : in std_logic; -- board ID st_spare2 : in std_logic; -- board ID dt_sel : out std_logic_vector(2 downto 0); rd_inc : out std_logic; -- increment block counter latch : out std_logic; dl_rd : out std_logic; next_data : out std_logic ); end component; component par2ser port (clk : in std_logic; rst : in std_logic; latch : in std_logic; dt_sel : in std_logic_vector(2 downto 0); tag : in std_logic_vector(4 downto 0); cmd : in std_logic_vector(4 downto 0); hdr : in std_logic_vector(31 downto 0); data_in : in std_logic_vector(15 downto 0); dlink : out std_logic ); end component; component latch16 port (clk : in std_logic; rst : in std_logic; enable : in std_logic; data_in : in std_logic_vector(15 downto 0); data_out: out std_logic_vector(15 downto 0) ); end component; begin ---------------------------------------------------------------------------- --COMPONENT INSTANTIATION ---------------------------------------------------------------------------- state: sm0_dlink port map(clk,rst,clk_30,data_vld,lst_data_l,dt_lng,rd_blk,blk_done,rd_evt_i, cmd_str,rd_dt_str,reg_data_vld,st_spare1,st_spare2,dt_sel,rd_inc, latch,dl_rd,next_data); shift:par2ser port map(clk,rst,latch,dt_sel,tag,cmd,hdr,data,dlink); dlink_latch:latch16 port map(clk,rst,data_vld_i,data_bus_i,data); ---------------------------------------------------------------------------- --PROCESS DECLARATION ---------------------------------------------------------------------------- sync_or: process (clk,rst) begin if (rst = '1') then lst_data_l <= '0'; dt_pres_l <= '0'; elsif (clk'event and clk = '1') then lst_data_l <= lst_data; dt_pres_l <= dt_pres; data_vld <= reg_data_vld; end if; end process; data_vld_i <= data_vld OR dt_pres_l; end rtl;