----------------------------------------------------------------------------
-- Lawrence Berkeley National Laboratory (c) 1997
-- BaBar Trigger Electronics
----------------------------------------------------------------------------
-- Description:  
--    This entity contains all logic for the clink fast control interface.
--    A serial data stream is recieved, comand, subcomand and data words are 
--    extracted and broadcast along with data and control strobes.
--    This entity might possibly profit from the nfl structure, but previous
--    versions have completed successful without the nfl prefix.
----------------------------------------------------------------------------
-- Structure:
-- clink_ctl
-- sm0_clink	-- state machine, controlling the latching of commands and
--		   data, as well as the strobe timing.
-- cmd_decode   -- main clocked process, decoding the comand and sub comand.
--		   This entity also produces the 30MHz alligned strobes from
--		   the strobe pimitives generated in sm0_clink.
-- ser2par	-- essentially a shift register to convert the serial data
--		   stream into a parrallel one.
-- latch16	-- latches the output of the shift register.
----------------------------------------------------------------------------
-- Timing:
--    Input of 1 bit serial data stream
--    Output of 16 bit data, various control strobes 
----------------------------------------------------------------------------
-- Author:   Armin Karcher
-- History:
--    Karcher    03/97 - First Version
--      Karcher	12-15-98	added block read                
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

----------------------------------------------------------------------------
--PORT DECLARATION
----------------------------------------------------------------------------

   
entity clink_ctl is
  port(
	clk 		: in  std_logic;	-- clk60 input, distributed
    	rst 		: in  std_logic;	-- global reset
	clk_30 		: in  std_logic;	-- clk30
        clink   	: in  std_logic;	-- serial data/command in
	rd_inc          : in std_logic;		-- next word during block read
	r_w_out	 	: out std_logic;	-- direction of internal bus
	data_out 	: out std_logic_vector(15 downto 0);  -- latched data
	adv_cmd_str     : out std_logic;	-- strobe on cycle 13 after 
				    -- the begin of a 12 bit command sequence
	cmd_str_30  	: out std_logic;	-- strobe aligned to clk30
	cmd_str  	: out std_logic;	-- strobe on cycle 14
-- command strobes are not sent on memory or register access cycles 
	blk_str	 	: out std_logic;	-- block address strobe 
						-- aligned to clk30
	ad_str 		: out std_logic;	-- address strobe 
						-- aligned to clk30
	wr_dt_str    	: out std_logic;	-- write data strobe
						-- aligned to clk30
	rd_dt_str    	: out std_logic;	-- read data strobe
						-- aligned to clk30
	clr_rd 	 	: out std_logic;	-- clear readout
	l1 	 	: out std_logic;	-- level1 accept
	rd_evt 	 	: out std_logic;	-- read event
	cal_str	 	: out std_logic;	-- calibration strobe
	sync 	 	: out std_logic;	-- sync
	reframe         : out std_logic;	-- clear input fifo
	usr_rst	 	: out std_logic;	-- user (subsystem) reset
	start_pl 	: out std_logic;	-- start record / playback
-- all command signals are valid from one tick before the cmd_str, until
-- one tick before the following cmd_strb.
	reg_rd 	 	: out std_logic;	-- read csr register
	reg_wr   	: out std_logic;	-- write csr register 
	-- ATTENTION!!! reg_wr has to be qualified by sel_csr to be valid.
	inc_add  	: out std_logic;	-- increment address 
	increment_add  	: out std_logic;	-- increment address
                                                -- for the address counter
	dt_lng  	: out std_logic;	-- data long (32 bit transfer)
	rd_blk 	 	: out std_logic;	-- read block
	blk_done 	: out std_logic;	-- read block done
	sel_csr  	: out std_logic_vector(2 downto 0); -- select csr
	cmd      	: out std_logic_vector(4 downto 0); -- latched command
	tag      	: out std_logic_vector(4 downto 0)  --   "  subcommand
      );
end clink_ctl;

architecture rtl of clink_ctl is
----------------------------------------------------------------------------
--SIGNAL DECLARATION
----------------------------------------------------------------------------
  signal strb_id: std_logic_vector(2 downto 0); -- type of strobe (address, 
				-- block address, read data, write data)
  signal shift_3: std_logic;	-- contents of shift register bit 3, a one
				-- will start the state machine.
  signal cmd_ext: std_logic;	-- external command (cmd_str will be driven)
  signal cmd_end: std_logic;	-- transfer/command end, about to terminate.
  signal cmd_lng: std_logic;	-- long command, more than the command word  
				-- (12 bits) will be read from the clink
  signal nxt_wrd: std_logic;	-- next word (command or data)
  signal latch_dt: std_logic;	-- latch data (1-tick-wide strobe)
  signal latch_t: std_logic;	-- latch subcommand (1-tick-wide strobe)
  signal latch_cmd: std_logic;	-- latch command (1-tick-wide strobe)
  signal c_str: std_logic;	-- internal version of adv_cmd_str
  signal data_in: std_logic_vector(15 downto 0);  -- non-latched data
  signal data_ordered: std_logic_vector(15 downto 0); -- takes care of 
				-- bit ordering (unlatched data)

----------------------------------------------------------------------------
--COMPONENT DECLARATION
----------------------------------------------------------------------------

  component  sm0_clink 
  port(
	clk 	: in std_logic;
	rst 	: in std_logic;
	shift_3 : in std_logic;
	cmd_ext : in std_logic;
	cmd_end : in std_logic;
	cmd_lng : in std_logic;
	nxt_wrd   : out std_logic;
	adv_cmd_str  : out std_logic;
	latch_dt_out : out std_logic;
	latch_t      : out std_logic;
	latch_cmd    : out std_logic
  );
  end component;

  component cmd_decode 
  port(
	clk 	: in std_logic;
	rst 	: in std_logic;
	clk_30 	: in std_logic;
	c_str   : in std_logic;
	nxt_wrd   : in std_logic;
	rd_inc    : in std_logic;	-- next word during block read
	latch_t   : in std_logic;
	latch_cmd : in std_logic;
	latch_dt : in std_logic;
	dt_in     : in std_logic_vector(15 downto 0);
	cmd_ext : out std_logic;
	cmd_end : out std_logic;
	cmd_lng : out std_logic;
	r_w_out : out std_logic;
	reg_rd 	 : out std_logic;
	rd_blk 	 : out std_logic;	-- read block
	blk_done : out std_logic;	-- read block done
	inc_add  : out std_logic;
	increment_add  : out std_logic;
	clr_rd 	 : out std_logic;
	l1 	 : out std_logic;
	rd_evt 	 : out std_logic;
	cal_str	 : out std_logic;
	sync_out : out std_logic;
	reframe  : out std_logic;	-- clear input fifo
	usr_rst	 : out std_logic;
 	start_pl : out std_logic;
 	dt_lng_out : out std_logic;
	wr_dt_str    : out std_logic;
	rd_dt_str    : out std_logic;
	ad_str       : out std_logic;
	blk_str      : out std_logic;
	cmd_str      : out std_logic;
	cmd_str_30   : out std_logic;
	sel_csr  : out std_logic_vector(2 downto 0);
	cmd      : out std_logic_vector(4 downto 0);
	tag      : out std_logic_vector(4 downto 0)
 );
  end component;

  component latch16 
  port	(clk 	: in  std_logic;
	rst 	: in  std_logic;
	enable 	: in  std_logic;
	data_in	: in  std_logic_vector(15 downto 0);
	data_out: out  std_logic_vector(15 downto 0)
        );
  end component;

  component ser2par 
  port	(clk 	: in  std_logic;
	rst 	: in  std_logic;
	clink 	: in  std_logic;
	data	: out  std_logic_vector(15 downto 0);
	shift3	: out std_logic
	);
  end component;

begin

----------------------------------------------------------------------------
--COMPONENT INSTANTIATION
----------------------------------------------------------------------------

  state: sm0_clink
port map(clk,rst,
	shift_3,
	cmd_ext,cmd_end,cmd_lng,
	nxt_wrd, 
	c_str,
	latch_dt,latch_t,latch_cmd
);

  decode: cmd_decode
port map(clk,rst,clk_30,
	c_str,nxt_wrd,rd_inc,
	latch_t,latch_cmd,latch_dt,
	data_in,
	cmd_ext,cmd_end,cmd_lng,
	r_w_out,
	reg_rd,rd_blk,blk_done,
	inc_add,
	increment_add,
	clr_rd,l1,rd_evt,cal_str,sync,reframe,usr_rst,start_pl,
 	dt_lng,
	wr_dt_str,rd_dt_str,ad_str,blk_str,cmd_str,cmd_str_30,
	sel_csr,
	cmd,
	tag
);

  latch:latch16
port map(clk,rst,latch_dt,data_ordered,data_out);

  shift:ser2par
port map(clk,rst,clink,data_in,shift_3);

data_ordered(15) <= data_in(0);
data_ordered(14) <= data_in(1);
data_ordered(13) <= data_in(2);
data_ordered(12) <= data_in(3);
data_ordered(11) <= data_in(4);
data_ordered(10) <= data_in(5);
data_ordered(9) <= data_in(6);
data_ordered(8) <= data_in(7);
data_ordered(7) <= data_in(8);
data_ordered(6) <= data_in(9);
data_ordered(5) <= data_in(10);
data_ordered(4) <= data_in(11);
data_ordered(3) <= data_in(12);
data_ordered(2) <= data_in(13);
data_ordered(1) <= data_in(14);
data_ordered(0) <= data_in(15);
----------------------------------------------------------------------------
--OUTPUT ASSIGNMENTS
----------------------------------------------------------------------------
  reg_wr <= nxt_wrd;
  adv_cmd_str   <= c_str;
end rtl;