vector clk30 clk30_0
vector clk15 clk15
vector clk8 clk8
vector bclk30 bclk30_0
vector bclk15 bclk15_0
vector bclk8 bclk8_0
vector fcdata data_io[15:0]
vector ad ad[31:0]
vector sel sel[10:1]



|clock clk30 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 
|clock clk8  0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1  
|clock clk15 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

report -memerrs -timing

|l cmd_str_30 rd_evt next_data data_width
|l ad_str blk_str wr_dt_str rd_dt_str inc_add
|l l1 usr_rst start_pl op_mode

|l en_in_mem in_play_rec
|l en_out_mem out_play_rec
|l spare1 spare2
|l st_spare1 st_spare2

h ~prgm

|h daq_format0

|stepsize 15ns

l vee

l gsr
h $1i2\reset
sim 100ns
l $1i2\reset
h gsr


wave control.wfm bclk30 bclk15 bclk8 
wave control.wfm  cmd_str_30 blk_str ad_str wr_dt_str rd_dt_str 
wave control.wfm  inc_add data_width
wave control.wfm  wr_addr wr_data
wave control.wfm rd_evt next_data  
wave control.wfm  rd_next_i rd_next_o rd_event_i rd_event_o
wave control.wfm  dt_pres lst_data
wave control.wfm  fcdata ad sel dnld read
wave control.wfm  clink cclk