vector clk30_0 clk30

clock clk30_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 

vector clk8_0 clk8
clock clk8_0  0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1  
 
stepsize 16.67ns

vector data d[15:0]
vector addr addr[23:0]
vector select sel[15:0]



l ad_str blk_str inc



l gsr
sim 100ns
h gsr



wave addreg.wfm clk30 clk8 data addr select
wave addreg.wfm ad_str blk_str inc_add inc
wave addreg.wfm en_addr wr_addr