L1 Global Trigger (GLT)
GLT Design
Documentations
- System level block diagrams and descriptions
- Global Trigger Module schematics:
- gltma , gltmb , gltm GLT top
level front/back/control signal flow
sections
- control ,
fc_intf ,
op_cntl
Fast control and Op-control
section & FPGA maps
- clocks , dirc_in ,
fp_led
Clock drivers, connection to DCC,
Front panel LEDs
- gltm_in
Input phi map signals from back plane
- dr1 , dr2
Delay/Combine/Playback FPGA maps (1=EMC+IFR, 2=DCH+X)
- mc FPGA map
for DCH/EMC phi match
- lkup1 , lkup2
Object count look up memories
- cuts , docut1, 2, 3, 4 Trigger
decision (do cut) diagram and FPGA maps
- trig_sel
, trig_sel1
, trig_sel2
Select-trigger
diagram and FPGA maps
- idaq , odaq FPGA
map for input/output DAQ & output playback memory
- output
Final stage trigger output fine delays
- All
schematics from Jeff's GLT page (SLAC only)
- Back of Crate Aux Board (GLTi) schematics:
- Floor plan and Layout:
Interfaces
Firmware and
Operations
Online and
Teststand
Offline
Analysis/Monitoring Utilities
Links and
Utilities
Su
Dong
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