L1 Global Trigger Final Design Review

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New/updated documents since PDR are marked with

Documentation:

New material for FDR
- Summary of design changes since PDR
Block Diagrams (Schematics, Module descriptions)
- System level block diagrams
- Global Trigger Module schematics:
  - gltma , gltmb , gltm GLT top level front/back/control signal flow sections
  - control , fc_intf , op_cntl Fast control and Op-control section & FPGA maps
  - clocks , dirc_in , fp_led Clock drivers, connection to DCC, Front panel LEDs
  - gltm_in Input phi map signals from back plane
  - dr1 , dr2 Delay/Combine/Playback FPGA maps (1=EMC+IFR, 2=DCH+X)
  - mc FPGA map for DCH/EMC phi match
  - lkup1 , lkup2 Object count look up memories
  - cuts , docut1, 2, 3, 4 Trigger decision (do cut) diagram and FPGA maps
  - trig_sel , trig_sel1 , trig_sel2 Select-trigger diagram and FPGA maps
  - idaq , odaq FPGA map for input/output DAQ & output playback memory
  - output Final stage trigger output fine delays
- Back of Crate Board schematics:
  - gltm_bpln GLT and back of crate backplane connections
  - gltm_input Back of crate card signal inputs
  - blt_in , pt_in , cal_in , ifr_in Signal receivers for BLT/PTD/EMC/IFR
- Floor plan and Layout:
System Description
- Global and Drift Chamber Trigger description (Implementation report):
Requirements Documents
- Full Trigger system requirements [L3 CDR V4.71 8-AUG-97]
- Global and Drift Chamber Trigger simulation justifications (Gehrig thesis)
Interface Specifications Documents
GLT Deliverable List

FDR Presentations:

Backup material:

DataFlow
- Feature Extraction [latest drafts (directory)] (Cathy Cretsinger)
- GLT DAQ data format: [Input DAQ][Output DAQ]
- GLT full memory/register map for DAQ and configuration: [gltmem_map]