Calorimeter L1 Trigger Final Design Review, June 18 1998

Review Committee
Committee Charge
Agenda

Updated Documentation From PDR:

• System Description
  • EMC Trigger: Description
• Block Diagrams and Schematics
  • Trigger Processor Board: Description, Block Diagram
  • TPB Schematics: [1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]
  • Trigger Processor Board: Floorplans Top Bottom
  • TPB Fast Control Xilinx Description, Block Diagram
  • TPB Algorithm Xilinx: Description Block Diagram Requirements Latency
  • TPB Formatter Xilinx: Description
  • TPB VME Xilinx: Description
  • Trigger Carrier Board: Schematic
  • Trigger Carrier Board: Floorplan
  • Custom Backplane Schematics: [All]
• External Interface Specifications Documents
  • Interface to EMC ROM/UPC
  • Interface to GLT
  • Interface to Fast Control: Protocol
  • Interface to DAQ: Full Trigger Description
  • Latency Estimate
• Internal Interface Specifications Documents
  • TPB Interface to Backplane [J2, J3]
  • TCB Interface to Backplane: [J3]
  • Algorithm Xilinx Interface to TPB: Pinout
  • TPB Interface to VME: Address Map
• Grounding and Shielding
  • See System Description
• Deliverables, Cost and Schedule
  • Project Specification
  • Detailed Schedule
• Requirements and Other Backup Documents
  • Full Trigger System Requirements
  • Calorimeter Trigger Electronics Requirements
  • Full Trigger Simulation Results (S.Gehrig Thesis)
  • TRB and EMB Documentation

New Documentation For FDR:

• System Description
  • Design Changes
  • Reliability Analysis
  • QA Plan
  • Installation and Commissioning
• Testing
  • Test Results
  • (Pre)Production Test Plan

Materials requested

List of review materials needed for FDR (text) Andy Lankford, February 1, 1997