August 12, 1998
						
Report for the Final Design Review of the BABAR Drift Chamber Trigger
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Committee:

David Coupal				coupal@slac.stanford.edu
Su Dong					sudong@slac.stanford.edu
Jean-Francois Genat			genat@lpnhp2.in2p3.fr
Ray Larsen				larsen@slac.stanford.edu
David MacFarlane, Chairperson		dbmacf@slac.stanford.edu
Jeff Olsen				jjo@slac.stanford.edu

Ex-officio:

Gerard Bonneaud
Gunther Haller
Walt Innes
Andy Lankford
Vera Luth

Date: August 7, 1998

Findings:

The Committee commends the DCT team on their development of a very
impressive design and testing framework for the DCH Trigger System, as well
as the depth and coverage of their testing program, both as already
implemented and as planned. The group seems to be aware of all of the
pitfalls ahead of them in building and testing the production run of boards.
They are taking steps to prevent any of the obvious problems. Since the
boards are entirely digital and most of the design is imbedded in firmware,
the tools for guaranteeing design accuracy and successful simulations are
particularly powerful and have served well. As a result of using these
integrated tools throughout the design(s), the group feels highly confident
in the accuracy of the designs.

Recommendations:

1. The DCT group should proceed with TSF production as soon as the remaining
first-article tests are completed. TSFI production can start right away.
Given the rather tight schedule, the TSF production loading should proceed
as soon as the remaining testing for the two preproduction boards are done.

2. Once the TSF production is in motion, it is also quite important to fully
test the 2 BLTs and complete the DCT->GLT interface test. The BLTs will be
very useful as a standard TRG module used in system tests with multiple
types of components in both LBL and SLAC for the dataflow.

3. Every effort should be made to have a significant fraction of the TSFs, a
BLT and GLT installed and operating by October 1. BABAR management should
see to it that the group gets sufficient technical support to complete the
production testing and debugging to meet the October 1 milestone. We agree
with the assessment that resources can be taken off the PTD testing and
applied to the TSF production, as part of the backup strategy. The true test
of the trigger system will only come when a full crate of modules are trying
to talk together. There may be unexpected problems there, which would be
better discovered as early as possible and resolved.

Comments and Observations:

1. The board designs appear to be robust, although ten layer fine pitch
layouts present a manufacturing risk, especially with a small run of boards
on a very tight timeline. Manufacturing mistakes must be avoided.  The group
may be a little over-confident in the amount of time needed to make the
boards functional. Bad solder joints or bridges must be found under a
microscope by sometimes painful searching, and internal problems with the
boards themselves, which may occur during the stresses of solder flow
loading, may be difficult to locate with all the parts loaded on the boards
from the beginning.  Perhaps the group has some good board troubleshooting
strategies for use at this stage but they did not explain them in detail.

2. The 5-way J2 connector contact problem seen on the 1st GLT may be an
isolated incident and easy to get around for just 1 board. However, given
that the same connectors are used in all DCT modules, the group should
exercise caution in this area by paying some attention to make sure there is
no such problem with the nearly 40 DCT production modules. It may be quite
awkward to fix properly even in a few cases of problems of this type.

3. Voltage and temperature margin testing has not been done. It would be
preferable that these be done at both the board level on initial functional
testing as well as at the loaded crate level.

4. No strategy for burn-in was discussed. It is suggested that loaded crates
of boards should be run for 72 hours at slightly elevated temperatures in
the lab before they go out to be installed. The lab is the place to do this,
not the field.

5. Interactions between boards in crates cannot be fully assessed without
more boards.  It would be wise to look with an oscilloscope at noise levels
on grounds and power lines to look for potential problem areas that may show
up later as random errors.  Just because a digital logic kind of test is
passed successfully does not mean that noise glitches or marginal levels of
fast signals may not be lurking close by.

6. The issue of the robustness of the TSF segment finding against excessive
detector noise or greater-than-expected backgrounds should be re-examined
over the coming months. Noise probably must weaken the algorithm when there
are hit inefficiencies at the same time. The most likely effect would seem
to be a non-optimal TSF vector direction which blurs the PT reconstruction
for the PTD. This is not likely to have serious consequences and hopefully
tuning the lookup table will be sufficient to achieve good optimization.
However, it would be useful to quantify this expectation in the light of PEP
II experience with backgrounds.