Overview
Trigger is logically a Digi-only simulation subsystem; No BBSIM/BOGUS
L1 Trigger consumes of GHits from DCH and Waveforms from EMC
Trigger packages have 25,000 lines of C++ and 35,000 lines of F77

Level of Detail
Gate-level real-time F77 electronics model matched to L1 hardware
Detailed L1 simulation can be skipped (cf. MDC1 reco production)
Fast simulation of L1A Tzero w. jitter is framework default

Needs from outside Trigger offline group
All Digi subsystems should use L1FctData Tzero and C++/f77 Fcs clocks
Digi <-> TC conversions from SVT, DCH, EMC and L1 (Online/Sim)
Closure on module sequence design (B. Jacobsen) rsn
Emc waveform timing: correctly obtained Fcs clocks (UK) queued
Dch waveform: instead of GHits, or with common ineffs (Dch) no plan!

Pending work

L1GltData accessors to the Digis (V. Serbo/T. Dignan) in progress
Separate trgGL from trgDC (V. Serbo) when time available
Configure TSF without running trgDC algorithms (LBL/L3) for MDC2
Hardware fidelity for trgDC TSF, PTD (D. Kasen/A. Meyer) in progress
Event Digis added for DC Trigger: BLT, PTD (LBL) as needed
Input DCH Digis/waveforms instead of GHits (LBL) waiting for DCH

Manpower hole: L1 QA/QC and global studies (1.0 FTE)
Integrate L1EmtSim into L1SimApp (T. Adye) in progress
Integrate persistent Digis into L1SimApp (RAL/LBL/SLAC) for MDC2

Manpower hole: L3 algorithms, benchmarks (1.0 FTE)
Consistent configuration of L1+L3 criteria (L3/OEP group) begun

Absolute Time: simulated with GEANT born-on time (a student) who?
Event Displays: displays with standard tools (students) who?
Production: not until new LER TURTLE rays (IR/PEP-II) summer