Overview
Trigger is logically a Digi-only simulation subsystem; No BBSIM/BOGUS
L1 Trigger consumes of GHits from DCH and Waveforms from EMC
L1 Trigger packages have 25,000 lines of C++ and 35,000 lines of F77
Digis stored to database as part of the SimApp Digi phase

Level of Detail
Gate-level real-time F77 electronics model matched to L1 hardware
Detailed L1 simulation can be skipped (cf. MDC2 single particles production)

Needs from outside Trigger offline group
All Digi subsystems should use L1FctData Tzero and C++/f77 Fcs clocks
Digi <-> TC conversions from SVT, DCH, EMC and L1 (Online/Sim)
Emc waveform timing: correctly obtained Fcs clocks (UK) queued
Dch waveform: instead of GHits, or with common ineffs (Dch) no plan!

Pending work

Redo TSF configuration.
Hardware fidelity for trgDC TSF, PTD (D. Kasen/A. Meyer) in progress
Event Digis added for DC Trigger: BLT, PTD (LBL) as needed
Input DCH Digis/waveforms instead of GHits (LBL) waiting for DCH

L1 QA/QC (A. Romosan) to begin

Manpower hole: L3 algorithms, infrastructure (1.0 FTE)
Consistent configuration of L1+L3 criteria (L3/OEP group) begun (TrgConfig)

Absolute Time: simulated with GEANT born-on time (a student) who?
Event Displays: displays with standard tools (students) who?