July 13, 1997

PRELIMINARY TEST PLAN FOR DRIFT CHAMBER TRIGGER
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Test Plan Strategy
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All boards contain only deterministic Digital Logic.
Can be tested with "Playback and Record" strategy.

To test core of each board:
 1) Download test patterns in Input Memory
 2) Play patterns through pipelined logic, recording results in Output Memory
 3) Read back Output Memory results and compare to expectations

To test interfaces, use Output Memory of upstream board to playback
into Input Memory.
DC Glink faked with STAR Rosebud VME module (makes programmable Glink
patterns).


Testing Phases
______________

Phase I				LBL
SVT test stand provides Fast Control and DAQ (old ROM)
Prototype boards on the bench

Phase II			LBL
Prototype Fast Control and DAQ (new ROM)
Prototype boards tested in one crate, with DIRC distribution system

Phase III			LBL
System test with multiple boards and crates
	A. Prototypes:	1 BLT,	 1 TSF, 1 PTD, 1 GLT, 1 TPB
	B. Preprod:	  -"-    2 TSF, 1 PTD,   -"-    -"-

Phase IV			LBL
Production validation using Phase-III hardware
			3 BLT, 28 TSF, 10 PTD, 3 GLT, 12 TPB

Phase V				SLAC
Installation testing in situ; maintenance in testing area