Calorimeter and Global Trigger Preliminary Design Review Report =============================================================== Review held November 11, 1997 at SLAC. Review Committee: Fred Bieser (LBNL), Mike Huffer (SLAC), Ray Larsen (SLAC), Krista Marks (LBNL), Helmut Marsiske (SLAC) and J.J. Russell (chair, SLAC). Final report submitted by J.J. Russell for the committee, November 13, 1997. EMC Trigger ----------- The EMC group has done a tremendous amount of work to complete the basic design in spite of many resource difficulties. The overall design of the TPBs together with the custom P3 backplane is well developed and will perform their function within the BaBar trigger system very well. They deserve congratulations for their collective achievements in reaching this milestone and for their strong collective efforts in preparing for the review. However, the committee is concerned about the testability and reliability of the main trigger board. It is clear that the group has been under great pressure to meet a BaBar testing milestone and, therefore, has hurried the board layout without sufficient time to fully take these issues into consideration. Given the trigger group's assertion that full board simulation is impractical, the committee feels the testability of the board is very important. To these ends, the committee specifically recommends: a. Spreading the components out. This will allow the use of clip-on test adapters, facilitate the addition of components as may be required and, in general, increase the accessability with a scope probe. The modest increase in line lengths between chips should not be a problem as they are data lines which should be resynchronized with clocks inside each chip (on the I/O pad of the FPGAs). b. Change as many components as possible to surface mount rather than thru-hole. This will improve their high-speed characteristics and help in routing. (Obviously PROMs remain in DIP sockets.) c. Try to put all components on the same side of the board. The added effort to produce and maintain double-sided boards usually outweighs any possible gain in circuit performance, particularly when there is ample space on the board. d. Add whatever drivers and traces that are required to make ALL 60Mhz clock lines source-terminated single load lines. This is relatively cheap and will eliminate a common source of performance failures. e. Make all 'like' FGPAs load from a single PROM in parallel. This will greatly simplify updates and the use of the Xilinx X-checker cable during debugging. f. Add additional uncommitted lines both between chips and to test-headers. If the design is pin limited, the lines to the test connectors can also be used as the spare lines between parts. This will allow internal Xilinx probing and circuit revisions without board modifications. g. Tie all the "DONE" pins from the FPGAs together so that they release from configuration at the same time. Tying an LED to the "LDC" pin of each FPGA will allow easy debugging should one FPGA not configure. h. Consider mocking up the cabling between the patch panel and the VME custom backplane. This area, illustrated in Figure 6, page 20, looks extremely dense. Special attention should be paid to strain relief and proper capture of the buried cables. These 'simple' problems always seem to get left to the last and can cause a wasteful and hurried iteration of redesign if not analyzed properly in the beginning. The committee also recommends that all FPGAs be fully placed, routed and simulated before the board is fabricated. This can proceed in parallel with the board layout, but should be completed before fabrication begins. While it was agreed that the trigger will support the physics goals, the committee questioned whether one would gain both flexibility and simplicity by keeping the phi granularity of the Y-sums indentical to the other sums. In summary, the committee is unanimous that further time should be taken before building the board. Given that even an optimistic projection fails to deliver a working system in time for the 1998 June installation, the committee recommends that a new schedule should be presented. This schedule should show, in as much detail as possible, the re-layout cycle for the board as well as related activities, such as the completion of the FPGA coding and simulations. The schedule should enumerate the specific manpower resources to be assigned to each task in order to assure the Trigger manager and BaBar management that the schedule is realistic and contains proper contingencies. If BaBar management perceives problems with the new schedule or the available resources, they should take appropriate measures to provide either schedule relief, such as a workaround plan for system testing, or find ways to lend additional resources to support an accelerated schedule. Global Trigger -------------- The overall design has progressed extremely well in all areas. The group is to be congratulated, especially for progress on the hardware, the state of the schematics, FPGA coding and simulations and the basic VHDL coding. However, the committee feels that all FPGAs be fully placed, routed and simulated before the board is released for fabrication. If BaBar management's policy is to demand that this work be completed before the board is released, the date suggested for completion may slip. The physics related issue of the flexibility and capacity of the decision logic was raised. It was felt that more of the DCH and EMC trigger primitives should be available for logic operations. While the present set of matches looks like a good opening set, future developments may dictate that the GLT have enough logic capacity, ie FPGA capacity, to handle a more complete set. If this proposal causes a major disruption for the ongoing layout, then an upgrade path should be seriously pursued. The main concern of the committee was the lack of detailed analysis of the system software effort needed to support the test plan and the lack of a detailed schedule showing the necessary resources to complete the test plan. This schedule should include proper contingency and workaround plans for the proposed system test.