Updated:  July 11, at 12:12pm

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Preliminary Design Review of the Level 1 Drift Chamber Trigger
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One full day, Monday July 14, 1997, in the SLAC Orange Room

The purpose of the review is to evaluate the readiness of the group to
release all designed DC Trigger prototype boards for fabrication.

All members of BaBar are invited to attend.

1. Closed Session	9:00 to  9:30

Charge and logistics				A.Lankford		30'

2. Early Morning	9:30 to 10:45

Physics requirements overview			F.Kral			15'
Block diagram overview of L1			R.Jared			20'
Interfaces to all L1 including latency		H.vdLippe		15'
Design method and board status			H.vdLippe		10'
Fast control interface and FPGA			A.Karcher		15'

3. Late Morning		11:00 to 12:40

Binary Link Tracker (BLT) boards		K.Dao			30'
Time during talk for reviewers on BLT					20'
PT Discriminator (PTD) boards and engine FPGA	S.Gehrig		30'
Time during talk for reviewers on PTD					20'

4. Mid day		12:40 to 2:00

Lunch
Committee meeting

5. Early Afternoon	2:00 to 3:20

Track Segment Finder (TSF) boards, FPGA summary	K.Marks			50'
Time during talk for reviewers on TSF					20'
DC Trigger project planning			F.Kral			10'

5. Late Afternoon	3:30 to 4:30

EM Trigger status				P.Dauncey		30'
GL Trigger status				Su Dong			30'

6. End afternoon	4:30 to 5:30

Report writing

7. Closeout Session	5:30 to 6:00

Review outcome