Overview
Trigger is logically a Digi-only simulation subsystem
Historical GEANT3 connection severed; No GEANT4
L1 Trigger consumes of GHits and geometry from EMC/DCH
Track Segment Finder Digi uses Fcs Tzero/clocks (cf. SVT Digi)
All other Digi subsystems should use C++/f77 Fcs clocks and Tzero

Level of Detail
Gate-level real-time f77 electronics model necessary for L1 design
Detailed L1 simulation can be skipped (cf. MDC1 reco production)
Fast simulation of L1A Tzero w. jitter is framework default

Needs
Time Class: absolute time class for L1A Tzero (Reco)
Time Stamp: simulated absolute time of event in .xdr file (T. Wenaus)
Digi to Raw Conversion: simulated data in Raw DataFlow format (Online/Sim)
Production: L3 may request huge backgrounds sets (G. Dubois-F.) Fall 1997

Pending work

Event Digis added for TPB (T. Adye) Summer 1997
Input EMC waveforms instead of GHits (T. Adye) Summer 1997
Rewrite trgEM in C++ (T. Adye) Fall 1997

Input new DCH GHits instead of GWirHits (LBL) 2 weeks, sometime in 1997
Event Digis added for BLT, PTD, GLT (LBL/SLAC) as needed by L3
Input DCH Digis/waveforms instead of GHits (LBL) Waiting for DCH
Rewrite trgDC and new separate trgGL in C++ (LBL/SLAC) ever?

Level 3 trigger algorithms exploration (A. Ryd, S. Yang, E. Frank) ongoing
Level 3 steering and infrastructure (C. Cretsinger) starts Summer 1997
Biggest manpower hole: L3 algorithms (1.0 FTE)

Package coordination, reco framework changes (A. Montgomery) forever 0.05 FTE
Switch to HepRandom, HepTuple and other BaBar reco standards like QA/QC (?)
Association of L1 primitives to EMC/DCH GHits/Digis (?) as pushed by L3