Front-End Assembly Test Bench

Version 0.3: 13-Nov-1997 by Masahiro Morii

Test Procedure

• Power check
• Initialization
• Elefant test mode
• FADC pedestal
• Discriminator offset
• Noise floor
• Analog gain (external calibration)
• Analog gain (internal calibration)
• Digital gain (external calibration)
• Digital gain (internal calibration)
• TDC resolution
• TDC linearity
• Trigger

• Is the power supply voltage/current normal?

Procedure

1. Plug on the FEA to the Test Bench.
2. Tighten the cap screws to secure the FEA on the radial bars, which provides cooling as well as the mechanical support.
3. Connect the power cable and the signal cable to the FEA.
4. Turn on the power (8V nominal). Measure the current.

Initialization

• Is it possible to write and read all the registers?
• Are the read-back values correct?

Procedure

1. Send command sequence for FEA reset, Elefant reset, TDC reset. Note that FEA reset must be followed by a few miliseconds of wait.
2. Read status. Check if Elefants locked.
3. Load all registers with default values. See below for list of registers and their default values.
4. Read back registers. Check all registers are correctly read back.
5. Reload all registers with default values.

Note: All registers must be loaded with the default values prior to each tests described below.

Elefant Test Mode

• Does the FEA transfer data in response to the Read command?
• Is the data structure correct?
• Is the data content correct?
• Are all data buffers (4 of them) ok?

Procedure

1. Set TestMode = 1 and ReadAll = 1.
2. Send Clear.
3. Repeat 4 times:
   1. Send L1Acc + Read.
   2. Read data.
   3. Check the data format and content. Make sure the buffer number is changing from 0 to 3.

FADC Pedestal

• Is the pedestal reasonable (between 0 and 10) ?
• Is the rms for each event (32 samples) small?
• Is the rms for many events small?

Procedure

1. Set ReadAll = 1.
2. Set discriminator threshold high, e.g. 500mV, to shut off the TDCs.
3. Repeat 10 times:
   1. Send L1Acc + Read.
   2. Read data and check the format.
   3. Calculate FADC pedestal and its rms. Check if the values are reasonable. Accumulate them in histograms.
4. Check the histograms for bad (e.g. unstable) pedestals.

Discriminator Offset

• Is the offset reasonable (80 ± 20 mV) ?
• Is the offset uniform (± 10 mV) in the FEA?

Procedure

1. Set DGain = 1. This reduces the digital gain to zero.
2. Scan the discriminator threshold from 40mV to 120mV in 5mV steps and repeat:
   1. Repeat 100 times:
      1. Send L1Acc + Read.
      2. Read data and check the format.
      3. Count the number of TDC hits in each channel. Accumulate it.
   2. Calculate average number of hits/event for each channel. Accumulate it as a function of threshold.
3. Find the threshold where the Nhit/event becomes less than 1. This should be close to the discriminator offset. Check if the values are within limits.

Noise Floor

• Is the noise floor reasonable (between xxx and yyy mV) ?
• Is the noise floor uniform (± 20 mV) in the FEA?

Procedure

1. Scan the discriminator threshold from 100mV to 200mV in 10mV steps and repeat:
   1. Repeat 100 times:
      1. Send L1Acc + Read.
      2. Read data and check the format.
      3. Count the number of TDC hits in each channel. Accumulate it.
   2. Calculate average number of hits/event for each channel. Accumulate it as a function of threshold.
2. Find the threshold where the Nhit/event becomes less than 0.1. This corresponds to the 45kHz noise floor. Check if the value is within limits.
3. Subtract the discriminator offset from the noise floor. This corresponds to 3 sigma noise amplitude. Check if the value is within limits.

Analog Gain (External Calibration)

The gain should be measured by integrating the waveform for 600ns = 9 FADC samples. The FADC is used in bilinear mode, i.e. the gain changes at code 32. Taking the nonlinearity of the preamplifier into account, we should parametrize the gain as a combination of 4-5 straight lines. Here, I assume that the gain is parametrized by two parameters A (below 32) and B (above 32).

• Is the gain for small signals reasonable?
• Is the linearity good enough up to the maximum input?
• The fitted gain curve must be recorded.

Procedure

1. Set discriminator threshold high, e.g. 500mV, and DGain = 1 to shut off the TDC.
2. Set ReadAll = 1.
3. Scan the external calibration amplitude from 10% to 100% of the expected FADC dynamic range in 10% steps and repeat:
   1. Scan the external calibration delay from 0 and 60ns in 6.67ns steps and repeat:
      1. Send L1Acc + Read.
      2. Read data and check the format.
      3. Calculate the charge integrated over 9 samples (600ns) as a function of A and B. The result must be a linear combination of A and B. Accumulate the coefficients.
   2. Calculate the average coefficients for A and B. Accumulate them as a function of external calibration amplitude.
4. Determine A and B by fitting.

Analog Gain (Internal Calibration)

By comparing the integrated charge measured by Elefant using the external and internal calibration, it is possible to correlate the CalDac value to the equivalent external input charge. The `gain' of the calibration circuit is then expressed as a capacitance (input charge / CalDAC voltage).

• Is the calibrator capacitance reasonable?
• Is the shape of the gain curve consistent with the external calibration?
• The calibrator capacitance must be recorded.

Procedure

1. Set discriminator threshold high, e.g. 500mV, and DGain = 1 to shut off the TDC.
2. Set ReadAll = 1.
3. Set CanRange = 0 (large signal).
4. Scan CalDac from 0 to 500mV in 50mV steps and repeat:
   1. Repeat 12 (must be a multiple of 4) times:
      1. Send Strobe + L1Acc + Read. For each cycle, change the delay between the Strobe and L1Accept by 1 sysclk.
      2. Read data and check the format.
      3. Calculate the charge integrated over 9 samples (600ns) as a function of A and B. The result must be a linear combination of A and B. Accumulate the coefficients.
   2. Calculate the average coefficients for A and B. Accumulate them as a function of external calibration amplitude.
5. Determine A and B by fitting. Compare the results with the values measured using the external calibration pulser. This should give two measurements of the internal calibration capacitor. Check the consistency.

Digital Gain (External Calibration)

• Is the digital gain reasonable?
• The gain curve must be recorded.

Procedure

1. Scanning the digital threshold from 200mV to 400mV in 50mV steps and repeat:
   1. Scan the external calibration amplitude at 10 points around the expected threshold level and repeat.
      1. Repeat 100 times:
         1. Send L1Acc + Read.
         2. Read data and check the format.
         3. Look for a TDC hit at the expected timing. Accumulate number of hits for each channel.
      2. Calculate the efficiency. Accumulate it as a function of external calibration amplitude.
   2. Determine 50% efficiency point by interpolating. Record it as a function of threshold voltage.

Digital Gain (Internal Calibration)

This calibration gives another capacitance value for the calibrator circuit. The value is, however, not the same as what was measured for the analog gain, because CalRange is set to small signal for this test.

• Is the calibrator capacitance reasonable?
• Is the measurement consistent at different threshold values?
• The calibrator capacitance must be recorded.

Procedure

1. Set CalRange = 1 (small signal).
2. Scanning the digital threshold from 200mV to 400mV in 50mV steps and repeat:
   1. Scan CalDac from 0 to 500mV in 50mV steps and repeat:
      1. Repeat 100 times:
         1. Send L1Acc + Read.
         2. Read data and check the format.
         3. Look for a TDC hit at the expected timing. Accumulate number of hits for each channel.
      2. Calculate the efficiency. Accumulate it as a function of external calibration amplitude.
   2. Determine 50% efficiency point by interpolating. Record it as a function of threshold voltage.
3. Compare the gain curve with what was measured using the external calibration pulser. This should give 5 mesurements of the internal calibration capacitance. Check the consistency.

TDC Resolution

• Is the efficiency 100%?
• Is the resolution good (<1 ns) ?

Procedure

1. Set the discriminator threshold at nominal value.
2. Repeat with external calibration amplitude at roughly 2 and 10 times the threshold level:
   1. Scanning the external calibration delay from 0 to 67ns and repeat:
      1. Repeat 100 times:
         1. Send L1Acc + Read.
         2. Look for a TDC hit at the expected time ±10ns.
         3. Accumulate the measured time if there is a hit.
      2. Calculate efficiency, average time and rms of the TDC hit.
   2. Calculate overall efficiency and average rms.

TDC Linearity

• Is the efficiency 100%?
• Is the TDC code frequency uniform?
• Does the TDC count increase monotonously with time?
• Is the TDC count linear?

Procedure

1. Set the discriminator threshold at nominal value.
2. Set the external calibration amplitude to roughly 10 times the threshold level.
3. Scan the external calibration delay from 0 to 67ns in 0.01ns steps and repeat:
   1. Send L1Acc + Read Event.
   2. Look for a TDC hit at the expected time ±10ns.
   3. If there is a hit:
      1. Accumulate the TDC code (0..63) in a hitogram.
      2. Accumulate the time residual, i.e. difference between the measured time (using 1.0417 ns/count) and the input delay.
4. Calculate the efficiency.
5. Calculate the frequency of each TDC code (0..63).
6. Plot the time residual vs the input delay. Calculate the spread and the rms.

Trigger

• Is the trigger consistent with the input?
• Do both TDC and FADC trigger work?

Procedure

1. Set TrigMode = 0 (TDC).
2. Set the threshold high (300mV) to reduce the accidental hits.
3. Set the external calibration amplitude to roughly 10 times the threshold level.
4. Repeat 10 times:
   1. Send NoOp.
   2. Read Trigger FIFO.
   3. Look for a trigger bit at the expected timing. Accumulate the hit.
5. Calculate efficiency for each channel. Check if it is consistent with the setting of the external calibration channel selection.
6. Set TrigMode = 1 (TDC).
7. Set FadcThr = 3 to reduce accidental hits.
8. Set the external calibration amplitude to roughly half the FADC dynamic range.
9. Repeat 10 times:
   1. Send NoOp.
   2. Read Trigger FIFO.
   3. Look for a trigger bit at the expected timing. Accumulate the hit.
10. Calculate efficiency for each channel. Check if it is consistent with the setting of the external calibration channel selection.

Address	Name	Size (bits)	Default
0	CalMask	128/144/192*	all 0	Calibration mask (1 = enable)
1	CalDac	12	0	Calibration DAC (1mV/count)
1	FetBias	12	1800	FET bias for Elefant (1800 = 1.8V)
1	CalRange	1	1	Calibration range select (1 = small signal)
2	DVT2	12	2200	Discriminator threshold low (2200 = 2.2V)
2	DVT1	12	2500	Discriminator threshold high (2500 = 2.5V)
2	DGain	1	0	Digital gain (0 = normal)
3	Vtop	12	4000	FADC top (4000 = 4.0V)
3	Vmid	12	1750	FADC middle (1750 = 1.75V)
3	Vbot	12	1000	FADC bottom (1000 = 1.0V)
3	Vref	12	1000	FADC pedestal (1000 = 1.0V)
3	ReadAll	1	0	Elefant sparce read out switch (0 = sparce read out; 1 = full read out)
3	TestMode	1	0	Elefant test mode switch (0 = normal mode; 1 = test mode)
3	Sparse	1	0	Elefant sparse readout source (0 = TDC; 1 = FADC)
3	TrigMode	1	1	Elefant trigger source (0 = TDC; 1 = FADC)
3	FadcThr	2	1	FADC delta trigger threshold (0..3 = more than 0..3 FADC counts)
3	AnaGain	2	0	FADC gain (0 = 5x; 1 = 10x; 2 = 20x; 4 = 40x)
4	Inhibit	18/18/24*	all 0	Elefant read out mask (0 = enable read out; 1 = inhibit read out)

*Sizes for inner/middle/outer FEA boxes.

Size	Content
1 byte	vROM clock counter
4 bytes	1st Elefant header
32 bytes	1st channel of 1st Elefant data
32 bytes	2nd channel of 1st Elefant data
	...
32 bytes	last channel of 1st Elefant data
4 bytes	2nd Elefant header
32 bytes	1st channel of 2nd Elefant data
	...
32 bytes	last channel of last Elefant data

Byte	Content
0	Bit 7 = unused; Bit 6:5 = TDC lock sum - Should be 0; Bit 4:3 = Board address (0..3); Bit 2:0 = Elefant address (0..5).
1	Hit map - 1 in bit 0..7 indicates at least one hit was recorded in channel 0..7. A hit can be either a TDC hit (Sparce = 0) or a FADC delta greater than FadcThr (Sparce = 1).
2	Elefant clock counter - This should be equal to the vROM clock counter + 1.
3	Bit 7 = unused; Bit 6:5 = Buffer number (0..3); Bit 4:0 = Trigger tag - This should be equal to the trigger tag sent with the L1Acc command.

Each byte in the 32-byte data consists of:

Bit	Contents
7	FADC delta	0 if FADC delta > FadcThr.
6	Data type	1 = TDC data; 0 = FADC data.
5:0	Value	6-bit Gray code if TDC data; 6-bit binary if FADC data.

• Is the TDC lock sum 0?
• Are the board/Elefant addresses physical?
• Is the clock counter consistent for all Elefant?
• Is the buffer number correct? It should be 0 after Clear Readout. It should increase by 1 (modulo 4) after each L1Acc.
• Is the trigger tag same as in the L1Acc?
• Is the hit mask correct? It should match the presense of either TDC hits or FADC delta (depending on Sparse) in each channel.
• Is the FADC delta bit (bit 7 of each data byte) correct? It should be 0 when the FADC data is greater than that of 2 clocks ago by more than the threshold value set in FadcThr.