Running the DRC Teststand at IR2

There is no internet browser installed on the SUN machine drcstand. To access internet (and in particular these instructions) ssh to another machine and start a browser from there.

To create a new xtc file (to change the number of boards in the front-end):

cd /nfs/bbr-srv02/dataflow/rdf/Drc/FE

start with existing .xtc file (Drc teststand loads whatever the softlink Drc3f_drcstand.xtc points to)

TestDrcRegisters {filename}.xtc > {anotherfilename}.txt

in the .txt file delete the two lines at the beginning that look like:

{IdQual: f5020.0} {IdQual: 0.0}
DrcRegisterTC containing 40 registers as follows:

put "FFFF"<CR> uppercase as a new line at the end

put {anotherfilename}.xtc at the end for the output file. IMPORTANT: make sure there is a carriage-return at the end of this line!

TestDrcRegisters < {anotherfilename}.txt (this will create the new xtc file)

point the softlink Drc3f_drcstand.xtc to the xtc file you want the ROM to read on configure.

The .txt file has 5 columns.The only column in the .txt file that you will have to change on the teststand is the fiberAmask (bitmask of boards in the front-end crate).

grp     regnum  val     fiberAmask  fiberBmask
0       0       8e3     de1c        0

odfElement numbering:

DCC is bit number 0

DFBs are bit numbers 2 through 15

The two slots to the right of the DCC do not hold DFBs.

The first slot that holds a DFB is bit number 2.

Changing the cycle file can affect register settings. Currently the 0x1da key is in Drc/Cycles/DrcT0_drcstand.xtc, and is linked to DrcLedFXteststand.xtc. If strange things start happening, that's a candidate to examine.

To run dataflow, bring up two windows on drcstand. In the first window, log on to bbr-reflin and then type "xyplex -f tt16-13". In the second window send the following commands:

setenv ODF_PLATFORM 13
setenv LD_LIBRARY_PATH /nfs/bbr-srv02/dataflow/package/shlib/SunOS58_sparc_WS6U1
/nfs/bbr-srv02/dataflow/0D/13/release/bin/SunOS58_sparc_WS6U1/fcgui -c 0x10000 -k 0x1da -t 0xffffffff&
/nfs/bbr-srv02/dataflow/0D/13/release/bin/SunOS58_sparc_WS6U1/eventtest -c 0x10000 -i 0 -d&

(above, SunOS58_sparc_WS6U1 is the current value of BFARCH, and may change someday in the future). Also, the key 0x1da looks like data taking. Vasia has said that the key 0x1d9 looks more like calibration (e.g. it doesn't send l1accepts up to the event level).

Click "Allocate"

Click "Arguments"

In the arguments window set BeginMajor to 0xffffff (this is N, and tells eventtest to dump out damage statistics every N events).

In the arguments window set BeginMinor to 0x10000 (this tells eventtest to dump out damage statistics for crate mask 0x10000).

In the arguments window click Apply followed by Close.

Click "Enable"

Damage statistics will be dumped by eventtest every time you Disable (by clicking on MinorCycle).

You get a 1Hz events by plugging a loopback lemo cable on the FCPM (rightmost fast controlboard) from SYSCLK/N to TRIG28. You get 4kHz events by plugging it into TRIG29.

To generate 5 2.7us spaced L1Accepts (a "recommended test"):

set the trigger mask in fcgui to 0

redo the configure transition

open the fcgui "calibration" menu

set "Counts" to 5

"Enable" the first command only, and select L1Accept

ensure that delay for the first command is set to 0

set "Cycle" to internal (the default)

now when you enable, 5 L1Accepts will be sent down.

Dataflow prints out details information about which board was out-of-synch/out-of-order for a few events. After these few, you either have to reboot the ROM, or type

odfOOSOOOPrint=1

at the ROM prompt (this will print out the detail for the next damaged event).